The present invention concerns the generation of syndrome bits within an error correcting and detecting circuit used in the transfer of data.
When transferring data within a communication system, it is often desirable to insure the integrity of the data transferred. To this end, various error detection and correction circuits have been utilized. In general, these error detection and correction circuits rely on correction bits sent in data packets with data bits. Data bits and correction bits are used to generate syndrome bits. Depending upon the particular error detection/correction code used, the syndrome bits are used to detect and/or correct errors which arise during data transfer. Such correction schemes serve to prevent the use of corrupted data and allows for correction of some errors in data transfer without resending data. For examples of prior art error detection and correction circuits, see U.S. Pat. No. 3,601,798 issued to M. Hsiao on Apr. 24, 1971 for Error Correcting and Detecting Systems; U.S. Pat. No. 3,648,239 issued to M. W. Carter et al. on Mar. 6, 1972 for System For Translating to and from Single Error Correction-Double Error Detecting Hamming Code and Byte Parity Code; U.S. Pat. No. 3,825,893 issued to D. Bosen et al. on Jul. 23, 1974 for Modular Distributed Error Detection and Correction Apparatus and Method; and, U.S. Pat. No. 4,450,561 issued to V. Goetze et al. on May 22, 1984 for Method and Device for Generating Check Bits Protecting a Data Word.